Assembly Syntax udiv regrs1, reg_or_imm, regrd
Operation Unsigned division. Concatenates %y register with low 32 bits of regrs1, performs division and writes result as 32-bit number into regrd; %y register is undefined afterwards.
Comments divide is an expensive operation; when possible, it should be avoided (see shift instructions)
Example udiv %r1, %r2, %r3
Example udiv %r1, 2, %r1