sdiv

Assembly Syntax

sdiv regrs1, reg_or_imm, regrd

op3

001111

Operation

Signed division. Concatenates %y register with low 32 bits of regrs1, performs division and writes result as 32-bit number into regrd; %y register is undefined afterwards.

Comments

none

Example

sdiv %r1, %r2, %r3

Example

sdiv %r1, -2, %r1

Instruction format

Instruction format

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